How can I reset this D-type counter in the attached Verilog-HDL code

manpreet Best Answer 2 years ago

I'm trying to create a d-type counter that resets when q0 = 0, q1 = 0 and q2 = 1.

I can make the value ADM trigger when the counter reaches this value but not reset ? Any helps appreciated thanks!

   // DEFINING D TYPE FLIP FLOP
  module D_FF(q,qb,d,clk,rst,pst);// pst or preset sets output q to 0(when pst=1)
                                 // rst resets to 1 takes priority 

 output q,qb;
 input d,clk,rst,pst;
 reg q;
 assign qb = ~q;
 always @ (posedge clk or negedge rst or negedge pst)
   case ({rst,pst })
     2'b00: q <= d;
     2'b01: q <= 0;
     2'b10: q <= 1;
     2'b11: q <= d;
   endcase
endmodule

The code below includes a commented out assign for the reset I do not understand why it will not work :/. //////////////// COUNTER CODE ///////////////////////////

module BIT_COUNTER(clk,reset,pst,q0,q1,q2,ADM);

wire d1,d2,d3;

input clk,reset,pst;
output q0,q1,q2,ADM;

D_FF dt0(q0,d1,d1,clk,reset,pst);

D_FF dt1(q1,d2,d2,d1,reset,pst);

D_FF dt3(q2,d3,d3,d2,reset,pst);


assign ADM = ( (q0 == 0) & (q1 == 0) & (q2 == 1));

// WHY CANT I RESET HERE USING ASSIGN ?
//assign reset = ( (q0 == 0) & (q1 == 0) & (q2 == 1));




endmodule

I've simulated it using the testbench and ADM will trigger but no reset

// Test Bench design to test the circuit under simulation..
module test;

reg clk,reset,pst; 


 BIT_COUNTER counter(clk,reset,pst,q0,q1,q2,ADM);




initial
  begin


    clk = 0;
    pst = 1;
    reset = 0;

   #10 pst = 0;





      #10 clk = ~clk; 
      #10 clk = ~clk; 
      #10 clk = ~clk; 
      #10 clk = ~clk; 
      #10 clk = ~clk; 
      #10 clk = ~clk; 
      #10 clk = ~clk; 
      #10 clk = ~clk; 
      #10 clk = ~clk; 
      #10 clk = ~clk;
      #10 clk = ~clk; 
      #10 clk = ~clk; 
      #10 clk = ~clk; 
      #10 clk = ~clk; 
      #10 clk = ~clk;
      #10 clk = ~clk; 
      #10 clk = ~clk; 
      #10 clk = ~clk; 
      #10 clk = ~clk; 
      #10 clk = ~clk;
    end  // end of test block.

endmodule  // end of test module.



 enter code here