An acceptable voltage range of a logic 1 for TTL

TTL (Transistor-Transistor Logic):A TTL input signal is defined as "low" when between 0 V and 0.8 V with respect to the ground terminal. A TTL input signal is defined as "high" when between 2 V and 5 V.if a voltage signal ranging between 0.8 V and 2.0 V is sent into the input of a TTL gate, there is no certain response from the gate and therefore it is considered "uncertain" (precise logic LEVELS vary slightly between sub-types and by temperature). TTL outputs are typically restricted to narrower limits of between 0.0 V and 0.4 V for a "low".TTL outputs are typically restricted to narrower limits of between 2.4 V and 5 V for a "high", providing at least 0.4 V of noise immunity. CMOS:For a CMOS gate operating at a power supply voltage of 5 VOLTS,The acceptable input signal VOLTAGES range from 0 volts to 1.5 volts for a “low” logic state and 3.5 volts to 5 volts for a “high” logic state.Acceptable output signal voltages range from 0 volts to 0.05 volts for a “low” logic state, and 4.95 volts to 5 volts for a “high” logic state: SpecificationsTTLECLCMOS FAN IN12-14> 10> 10FAN OUT102550power dissipation (mW)10750.001Noise margin0.50.16(least)1.5 (highest)Propagation delay(NS)10>315Noise immunityvery goodgoodexcellent