In CMOS designs, why size of PMOS is kept larger than size of NMOS?

To maximize the switching speed of a logic gate, for example, an INVERTER, it is best if the rise and fall time of the logic gate’s output signal is the same. For this to occur, the top side transistors of the logic gate must switch current into the output of the logic gate at the same magnitude as the low side transistors. SINCE PMOS transistors (high side) have approximately half the mobility of NMOS transistors (low side), it is necessary to add two parallel PMOS DEVICES to the high side to achieve the equivalent magnitude currents.In saturationNMOS:\({I_{{D_N}}} = {\mu _n}\;{C_{ox}}\FRAC{\omega }{L}{\left( {{V_{GS}} - {V_T}} \right)^2}\;\;\) PMOS\({I_{{D_P}}} = {\mu _p}{C_{ox}}\frac{\omega }{L}{\left\{ {{V_{SG}} - \left| {{V_T}} \right|} \right\}^2}\) Cox and voltage are the same for both side, when \({I_{{D_N}}} = {I_{{D_P}}}\) \({\mu _p} \times \frac{{{\omega _p}}}{L} = {\mu _n} = \frac{{{\omega _n}}}{L}\) ∵ μ­n ≃ (2.5 – 2.7) μpConsidering the same length as it is a fixed constraint for the circuit.ωp ωN or, \({\omega _p} \simeq \left( {2.5\;to\;2.7} \right){\omega _N}\) that’s why we take PMOS size greater than N-MOS