In CMOS implementation of a NAND gate:

CMOS is a combination of NMOS & PMOS.NAND gate can be implemented using two PMOS in parallel and two NMOS in series as shown:Observations:1) When VA & VB are high at +VDD (5V), then the PMOS will be open-circuited and two NMOS will be short-circuited, the output will be short-circuited to ground and PRODUCES a ZERO (0V) output.2) When any of the input is low (0 V), the CORRESPONDING PMOS will be shorted and NMOS will be open, the output is shorted to VDD, i.e. it produces a high output.NAND Gate:It is the combination of AND Gate followed by NOT Gate.When the two inputs A and B are high, then output y is low, otherwise, it is high.ABY001011101110